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Core Configuration
4.4 Configuring Interrupts
DSP56311 interrupt handling, like that for all DSP56300 family members, is optimized for DSP
applications. Refer to the sections describing interrupts in Chapter 2 , Core Architecture
Overview , in the DSP56300 Family Manual . Two registers are used to configure the interrupt
characteristics:
Interrupt Priority Register-Core (IPRC)—Programmed to configure the priority levels for
the core DMA interrupts and the external interrupt lines as well as the interrupt line trigger
modes
Interrupt Priority Register-Peripherals (IPRP)—Programmed to configure the priority
levels for the interrupts used with the on-chip peripheral devices
The interrupt table resides in the 256 locations of program memory to which the PCU vector base
address (VBA) register points. These locations store the starting instructions of the interrupt
handler for each specified interrupt. The memory is programmed by the bootstrap program at
startup.
4.4.1
Interrupt Priority Registers (IPRC and IPRP)
There are two interrupt priority registers in the DSP56311. The IPRC ( Figure 4-3 ) is dedicated to
DSP56300 core interrupt sources, and IPRP ( Figure 4-3 ) is dedicated to DSP56311 peripheral
interrupt sources.
23
22
21 20 19 18 17 16 15 14 13 12
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
11
10
9
8
7
6
5
4
3
2
1
0
IDL2
IDL1 IDL0 ICL2
ICL1
ICL0
IBL2
IBL1
IBL0
IAL2
IAL1
IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)
DSP56311 User’s Manual, Rev. 2
4-14
Freescale Semiconductor
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